H.264中采用FPGA实现的变长码编解码器  

Encoder and Decoder of Variable Length Coding in H.264 with FPGA Implementation

作　　者：陆伊[1] 骆勇俊[2] 杨爱良[1] 

机构地区：[1]中国航空无线电电子研究所,上海200233 [2]海军驻上海地区航空军事代表室,上海200233

出　　处：《航空电子技术》2009年第3期34-38,共5页Avionics Technology

摘　　要：变长编码广泛用于各种编码方案中。H.264中采用了基于上下文的自适应变长编码(CAVLC),其编解码设计的关键技术是快速搜索和匹配结构复杂的码表。本文结合CAVLC特点,改进了编码算法的码字存储方式方法,分析传统的变长码解码算法,提出一种基于ROM快速寻址的解码算法。在Vertex4FPGA上的验证结果表明,该方案较好的权衡了面积和速度性能,降低了设计的复杂度。Variable Length Coding is broadly applied in kinds of coding plan, and in H.264 standard, Context-based Adaptive Variable Length Coding （CAVLC） is adopted. The key technologies of encoder and decoder are fast searching and matching the code tables with complex structttre. In the paper, after analysis the character of CAVLC, an improved VLC storage method using in encoder is proposed, after analysis of traditional arithmetic, arithmetic based on fast ROM addressing is proposed to use in decoder. The verification result on Vertex4 FPGA indicates that this plan balances the area and speed performance, and reduces the complexity of design.

关 键 词：CAVLC 码字压缩存储 重排序 ROM寻址 

分 类 号：TN911.73[电子电信—通信与信息系统]