数字化DC-DC变换器的控制器结构优化  

Controller architecture optimization method for digitally controlled DC-DC converters

作　　者：王超[1] 张东来[1] 沈毅[2] 

机构地区：[1]哈尔滨工业大学深圳研究生院,广东深圳518055 [2]哈尔滨工业大学航天学院,黑龙江哈尔滨150001

出　　处：《电机与控制学报》2009年第5期695-701,共7页Electric Machines and Control

摘　　要：针对现有的数字化DC-DC变换器的控制器结构,基于FPGA从DPWM控制策略、采样控制策略和计算控制策略方面对系统进行优化。控制器运算单元采用浮点乘累加器实现,保证了运算精度,同时提出实时运算控制策略和基于查表法的整型转浮点和浮点转整型转换器,从而减少了开关管导通时间的计算时间;提出优化的采样和PWM策略,能够消除采样保持和计算过程所带来的控制器输出延迟;采用基于二阶Σ-Δ的DPWM和双模式补偿算法,消除极限环的同时保证了控制器的快速的动态响应能力。实验证明:利用上述方法能够得到具有快速动态响应而又无极限环现象的稳定输出。An optimized architecture of a digital controller was presented. It was described at functional level and designed with FPGA （Field-Programmable Gate Array）. Optimization of the system included DPWM （Digital Pulse Width Modulation） scheme, sampling scheme and computation scheme. Computational accuracy was guaranteed by floating-point arithmetic based on muhiply-accumulative unit. At the same time, fast integer-float and float-integer converters were developed based on look-up tables and realtime computation scheme which can greatly reduce the duty-time computation clocks brought by the floating-point operations. Sampling and PWM （Pulse Width Modulation） scheme were optimized to avoid PWM delay caused by sampling and hold the computation process. High precision digital pulse-width modulator based on second-order sigma-delta concept （∑-△DPWM） and dual-mode compensator method were implemented here to eliminate steady Limit-Cycle and at the same time to maintain fast dynamic response. Experimental results show that the architecture can bring a stable no-limit-cycle output with fast dynamic response.

关 键 词：可编程逻辑阵列 数字脉宽调制控制器 DC-DC变换器 

分 类 号：TM46[电气工程—电器]