基于Mastrovito乘法的字串行特征二域乘法器  

Digit-serial binary field multiplier based on Mastrovito multiplication

作　　者：陈刚[1] 白国强[1] 陈弘毅[1] 

机构地区：[1]清华大学微电子学研究所,北京100084

出　　处：《清华大学学报（自然科学版）》2009年第10期1684-1687,共4页Journal of Tsinghua University(Science and Technology)

基　　金：国家自然科学基金资助项目(60576027);国家"八六三"高技术项目(2006AA01Z415)

摘　　要：针对目前常用的最低字优先字串行特征二域多项式基乘法器存在冗余计算的问题,提出了一种更加高效的最低字优先字串行乘法器。首先讨论了多项式模乘和Mastrovito乘法与最高位优先和最低位优先位串行乘法之间的关系,然后根据讨论发现的结果,将Mastrovito乘法器转变为字串行的形式,推导出新的最低字优先字串行乘法器。对综合所得的门级网表的比较显示:该乘法器的面积延时积比目前常用的最低字优先字串行乘法器小6.16%,比常用的最高字优先字串行乘法器小2.69%。A more efficient least-significant-digit first （LSD-first） digit-serial multiplier was developed to reduce redundant computations existing in commonly used LSD-first digit-serial polynomial basis multipliers over binary fields. The relationships between polynomial modular multiplication and Mastrovito multiplication, and most significant-bit-first and least-significant-bit-first bit-serial multiplications were analyzed to derive an LSD-first digit-serial multiplier by transforming a Mastrovito multiplier into a digit-serial form. A comparison between synthesized gate-level net-lists shows that the area-delay-product of this multiplier is 6.16% less than that of commonly used LSD-first digit-serial multipliers and is 2.69% less than that of commonly used most significant-digit-first digit serial multipliers.

关 键 词：串行乘法器 Mastrovito乘法 特征二域 多项式基 

分 类 号：TN432[电子电信—微电子学与固体电子学]