基于钟控神经MOS管的多值双边沿D触发器设计  

Design of multi-valued double-edge-triggered D flip-flop based on clock-controlled neuron MOS transistor

作　　者：张跃军[1] 汪鹏君[1] 

机构地区：[1]宁波大学电路与系统研究所,浙江宁波315211

出　　处：《浙江大学学报（理学版）》2009年第5期534-538,共5页Journal of Zhejiang University（Science Edition）

基　　金：国家自然科学基金资助项目(60776022);浙江省科技计划资助项目(2008C21166);浙江省"新苗人才计划"项目(2007R40G2070013)

摘　　要：通过对钟控神经MOS管特性和冗余抑制技术的研究,提出了一种新型多值双边沿D触发器的设计方案.该方案利用钟控神经MOS管多输入栅加权信号控制、浮栅上的电容耦合效应及具有对浮栅进行初始化并将数据保存在浮栅上等特性,实现D触发器的多值输出.与传统触发器相比较,此多值触发器不但减少时钟冗余信号,降低电路功耗,提高电路效率,而且无需改变电路的结构就可实现不同基的多值D触发器.最后,采用0.25μmCMOS工艺,利用PSPICE模拟验证了所设计的电路具有正确的逻辑功能,并与相同功能多值D触发器比较,多值双边沿D触发器具有明显的低功耗特性.Through the research on the characteristics of clock-controlled neuron MOS transistor and the principles of redundancy-restraining technique, a design scheme of multi-valued double-edge-triggered D flip-flop is presented. The clock-controlled neuron MOS transistor＇s characteristics, including multiple-input signals threshold operation, the floating gate capacitance coupling effect and initiation of floating gate and storing the data in floating gate, were integrated together to implement this proposed scheme. Compared with the conventional multi-valued D flip-flop, this flip-flop has the characteristics of reduction the redundant leap of clock, low power consumption and fast speed, etc. Moreover, it is not necessary to change the circuit structure in order to realize multi-valued D flip-flop of different radixes. PSPICE simulation results verified the valid functionality and the significant low-power characteristic of the designed circuits.

关 键 词：钟控神经MOS管 双边沿D触发器 多值触发器 冗余抑制 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]