面向VLIW结构的寄存器压力敏感表调度算法  

Register-pressure-sensitive list scheduling algorithm for VLIW architectures

作　　者：王红梅[1,2] 王敏[1,2] 张铁军[1] 单睿[1] 侯朝焕[1] 

机构地区：[1]中国科学院声学研究所,北京100190 [2]中国科学院研究生院,北京100039

出　　处：《计算机应用研究》2009年第11期4039-4041,共3页Application Research of Computers

基　　金：国家"973"计划资助项目(G1999032900)

摘　　要：为了改善寄存器压力问题,提出一种寄存器压力敏感的指令调度算法。该算法在传统表调度算法的基础上采用关键路径为优先级函数,并考虑在寄存器压力区域内调整非关键节点的调度时机,在应用程序性能不损失的情况下达到了减小寄存器压力的目的。Register pressure occurs when the amount of available physical registers is smaller than that intermediate presentation needs, then it often forces compiler to insert extra spill/fill operations into assembler code which both decreases performance of applications and increases processor＇ s energy consumption. This paper proposed a register-pressure-sensitive instruction scheduling algorithm based on list scheduling to resolve this problem. This algorithm not only considered nodes on critical path as major factor of the priority function, but also tried to adjust issue time of nodes on uncritical path. It finally achieved less register pressure with nearly no performance loss.

关 键 词：寄存器压力 表调度算法 指令调度 寄存器分配 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]