1.8V 10bit 40MS/s的流水线模数转换器  

A 1.8 V 10 bit 40 MS/s Pipelined ADC

作　　者：谭晓[1] 郭桂良[1] 杜占坤[1] 阎跃鹏[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《半导体技术》2009年第10期1046-1050,共5页Semiconductor Technology

摘　　要：设计了一个10bit,40MS/s流水线模数转换器,适用于无线传感器网络(WSN)嵌入式芯片中。基于对电容失配的非线性影响的分析,提出了每级多比特的结构,使ADC具有很好的线性度。片内集成了参考电压源,大大减少了外围电路的数量。芯片采用SMIC0.18μmCMOS工艺实现,在40MS/s采样率下,电路微分非线性(DNL)最大0.42LSB,积分非线性(INL)最大0.93LSB,有效精度(ENOB)最高达9bit。电路使用1.8V电压供电,核心面积1.5mm2,核心电路功耗73mW。A 10 bit 40 MS/s pipelined ADC was presented, which was used in the wireless sensor network embedded chip. Based on the analysis of the capacitor mismatch on the linearity, a muhibit-per-stage architecture was proposed to promote the linearity of the whole circuit. References voltage circuits were integrated on-chip and the number of off-chip devices was reduced greatly. The chip was fabricated in SMIC 0.18 ~tm CMOS process. The ADC achieves a maximum differential nonlinearity of 0.42 LSB, a maximum integral nonlinearity of 0.93 LSB, and a maximum effective number resolution of 9 bits. It works at 1.8 V. The core of the ADC occupies 1.5 mm^2 Si area and dissipates 73 mW.

关 键 词：无线传感网 模数转换器 流水线 电容失配 参考电压源 

分 类 号：TN432[电子电信—微电子学与固体电子学]