基于锁的Cache一致性协议的硬件优化策略  

Optimization of lock based Cache-coherence protocol by hardware

作　　者：蔡晔[1,2] 史岗[1] 

机构地区：[1]中国科学院计算技术研究所,北京100080 [2]中国科学院研究生院,北京100080

出　　处：《高技术通讯》2009年第9期933-938,共6页Chinese High Technology Letters

基　　金：863计划(2006AA010201);国家自然科学基金(60736012)资助项目。

摘　　要：对一种基于锁的Cache一致性协议的开销进行了评估和分析,并结合一款处理器接口的设计,实现了一种分布式内存结构上的远程内存共享机制。该机制能提高处理器机间的通讯性能,降低一致性协议中的通讯延迟,同时通过硬件锁对协议中的同步开销进行优化,避免锁管理器节点陷入处理程序而减少同步等待时间。实际测试结果表明,通过硬件优化的软件Cache一致性协议基本操作的性能得到极大的提高,并在实际应用上具有更好的加速比和可扩展性。The overhead of a lock based cache coherence protocol was evaluated and analyzed. To reduce the major communication overhead, a fast shared memory-accessing method was proposed on a distributed memory architecture and implemented in design of a reduced instruction set computer （RISC） processor. And a hardware lock scheme was also proposed to reduce the synchronization overhead. Based on this scheme the overhead of trapping to service program of lock manager machine can be eliminated and the waiting time during the synchronization period can also be reduced. The experimental result shows that the lock-based cache coherence protocol which optimized by the proposed hardware schemes has the better parallel speedup and scalability.

关 键 词：一致性协议 锁 同步 消息传递 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]