AFDX-ES芯片设计中主机端接口的设计与验证  

Design and verification of AFDX-ES SoC chip based on host interface

作　　者：曹庆年[1] 强新建[1] 田泽[1,2] 

机构地区：[1]西安石油大学计算机学院,陕西西安710065 [2]中国航空计算技术研究所,陕西西安710068

出　　处：《西北大学学报（自然科学版）》2009年第5期761-764,共4页Journal of Northwest University（Natural Science Edition）

基　　金：陕西省自然科学基金资助项目(2006F44)

摘　　要：目的基于ARM9的AFDX-ES芯片的PCI主机接口的设计与逻辑验证。方法以软硬件协同设计方法学、验证方法学为指导,提出了以PowerPC处理器为核心的主机端软硬件平台下SoC软硬件协同方法,并搭建了基于芯片的FPGA原型验证平台。结果通过主机上VxW orks对AFDX-EX芯片上资源进行管理以及对各功能模块进行功能调用,有效地验证了SoC主机接口逻辑功能的正确性。结论文中方法设计合理,运行可靠,可以应用于类似芯片的设计中。Aim For ARM9-based AFDX-ES-chip PCI host interface design and logic verification. Methods Under the direction of co-verification and design methodology of hardware and software, a SoC software and hardware co-design method with a power PC processor core on host-side software and hardware platform is put foward,and a chip-based FPGA prototype verification platform is built. Results By runing and function calling each function module and resources management of AFDX-ES chip in VxWorks,the correctness of SoC host interface logic function is verified effectively. Conclusion This method is a reasonable design;reliable operation, and can be applied to a similar chip design.

关 键 词：SOC POWERPC ARM 协同设计 协同验证 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构]