A Novel GGNMOS Macro-Model for ESD Circuit Simulation  

作　　者：JIAO Chao JIAO Chao YU Zhiping YU Zhiping[1] 

机构地区：[1]Institute of Microelectronics, Tsinghua University, Beijing 100084, China [1]Institute of Microelectronics, Tsinghua University, Beijing 100084, China

出　　处：《Chinese Journal of Electronics》2009年第4期630-634,共5页电子学报（英文版）

基　　金：This work is supported by the National Natural Science Foundation of China （No.90307016）.

摘　　要：A novel macro-model for ESD circuit sim- ulation with only five fitting parameters is proposed. In this model a new topology and a new multiplication factor equation are proposed as well as the extracting method. This modeling approach greatly reduces time and effort required for circuit design while making use of GGNMOS （Gate-grounded NMOS） as ESD （Electrostatic discharge） protection~ which is widely used for integrated circuits to protect IOs and power rails. The DC characteristics of GGNMOS and transient behavior of GGNMOS under HBM （Human body model） stress are simulated using both our macro-model and two-dimensional device simulator, Taurus （Synopsys）. Good agreement has been obtained.

关 键 词：Gate-grounded-NMOS Electrostatic dis- charge  ESD modeling  Human body model  Snapback. 

分 类 号：TN402[电子电信—微电子学与固体电子学] U491.112[交通运输工程—交通运输规划与管理]