1-bit采样超宽带系统关键模块的ASIC实现与优化  

Implementation and Optimization on Key Modules of 1-bit Sampling UWB System

作　　者：贝旻[1] 张在琛[1] 尤肖虎[1] 

机构地区：[1]东南大学信息科学与工程学院移动通信国家重点实验室,210096

出　　处：《中国电子商情（通信市场）》2009年第5期25-30,共6页

摘　　要：本文研究了一种新的超宽带系统方案-1-bit采样的超宽带系统方案，在接收端它通过对接收信号进行1-bit采样、同步、信道估计和信号检测来恢复出发送信号。文中从系统整体对脉冲超宽带信号产生与接收的处理进行了原理分析，然后通过HDL建模设计了系统和模块的功能，对接收核心模块进行了ASIC设计，并通过门控时钟、操作数隔离、门级功率优化的方法对设计进行了综合优化，显著降低了系统的功耗。This paper provides a new ultra-wideband system solution 1-bit sampling ultra-wideband system. At the receiving end, it receives signals through the 1-bit sampling, synchronization, channel estimation and signal detection to recover a transmitted signal. This paper investigates the impulse UWB signal generation and reception, and provides the system and module design for the UWB system with Verilog language. Then the paper implements the design of key module based on ASIC, and optimizes the design through clock gating, operand isolation, gate-level power optimization method, significantly reducing system power consumption.

关 键 词：超宽带 1-bit采样 ASIC 信道估计 低功耗 

分 类 号：TN492[电子电信—微电子学与固体电子学]