软判决Fano译码算法的FPGA实现  

Software Decision Decoding of Fano Decoding Algorithm and the FPGA Implementation Method of Its Decoder

作　　者：侯文姝[1] 蒋宇中[1] 

机构地区：[1]海军工程大学电子工程学院,湖北省武汉市430033

出　　处：《信息化研究》2009年第10期14-17,共4页INFORMATIZATION RESEARCH

摘　　要：Fano译码算法一般采用软件实现,受制于计算机的结构,译码速度较慢。为大幅度提高译码速度,研究软判决Fano译码算法的全硬件实现方案,即采用AHDL(Altera硬件描述语言)设计软判决Fano译码译码器,使用FPGA(现场可编程门阵列)予以实现。介绍了总体结构,重点描述构建Fano软判决译码器关键部件——状态机的设计。实测数据表明,在相同时钟频率条件下,软判决Fano译码算法的全硬件实现比软件方案至少快20倍。Limited by the architecture of computer, the decoding speed of software implementation of Fano decoder is slow. To improve the decoding speed, we studied the hardware implementation of sequential decoder. An Field Programmable Gate Array （FPGA） prototype of the decoder is built, using Altera Hardware De- scription Language （AHDL）. The state machine, the key part of Fano decoder, is described in detail in this paper. The result shows that the hardware implementation of sequential decoder has speed faster than that of the software implementation by at least 20 times with the same frequency.

关 键 词：Fano算法 序列译码 FPGA 

分 类 号：TN911.2[电子电信—通信与信息系统]