基于CPLD的加速度测试仪设计  

Design on testing and measuring system for acceleration based on CPLD

作　　者：彭丹[1] 雷华明[1] 

机构地区：[1]上海交通大学仪器科学与工程系,上海200240

出　　处：《电子测量技术》2009年第10期114-116,120,共4页Electronic Measurement Technology

摘　　要：在航空航天、海洋工程、仪器仪表、轻工和环保等行业应用中,为保证产品能最有效工作,常常需要对一些高冲击下的信号进行测试分析。结合存储测试技术,本文设计了一种以CPLD为核心、捕获高冲击下测试加速度信号的仪器,并给出了测试加速度的时序逻辑与控制电路。最后,通过QuartusII软件对系统进行了仿真,仿真结果显示,设计的电路满足了加速度测试的要求。此外,本文设计电路从节能方面考虑,应用能耗较低的新型芯片,并特别设计了电源管理电路,实现了整个系统的低能耗。In some fields, such as aerospace, ocean engineering, instruments, light industry, environmental industry and etc, it＇s necessary to measure signals under high attack to ensure the effective work of the products. By referring to the storage technology, this paper has designed an apparatus, which is used to get the high-shocking accelerate signal. It takes CPLD as the core control unit, with which the sequential logic and control circuit of this system is designed and implemented by using CPLD. The functional simulation of the apparatus is performed in QuartusII software. The result is satisfactory, and can meet the requirements of the testing system. By the consideration of energy-saving of the circuits, emphasis is also put on the choose of new chips and the special design for the power control circuit, through which the low-power consumption of the system is realized.

关 键 词：加速度 时序控制 负延时 低功耗 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]