一种基于DDS+PLL结构的频率合成器的设计  

Design of frequency synthesizer based on DDS+PLL

作　　者：蒋涛[1] 唐宗熙[1] 张彪[1] 

机构地区：[1]电子科技大学电子工程学院,成都610054

出　　处：《电子测量与仪器学报》2009年第10期91-95,共5页Journal of Electronic Measurement and Instrumentation

摘　　要：讨论了一种输出频带宽、跳频速度快、相位噪声低、频率分辨率高的频率合成器的设计方法。该设计采用DDS+PLL结构,在对单片机的输出信号进行电平转换后采用并行数据控制方式对DDS芯片进行置数,并通过仿真软件设计了环路滤波器和DDS后级低通滤波器,改善了输出信号的相位噪声和杂散性能。基于该方法研制实现了输出频率范围为700～1200MHz的宽带频率合成器,实验结果表明该频率合成器输出功率大于+4dBm,环路锁定时间为14μs,输出信号相位噪声优于-94dBc/Hz@1kHz,近端杂散抑制度大于-59dBc。A method to develop a frequency synthesizer with wide band, fast frequency switching speed, high frequency resolution and low phase noise is discussed. This method is based on the DDS＋PLL structure. Parallel programming mode is used and the signal from the MCU is been switched to control DDS. The loop filter is optimized to have low phase noise performance and the computer emulation technology is used to design the lowpass filter. A frequency synthesizer sweeping from 700MHz to 1200MHz is been made. Experimental result shows that the output power is over ＋4dBm, frequency switching time is 14μs, phase noise is better than-94dBc/Hz@1kHz and the spurious suppression is more than-59dBc.

关 键 词：DDS 锁相环 宽带 

分 类 号：TN74[电子电信—电路与系统]