具有分时背景抑制功能的单元电路设计  

Design of pixel readout circuit with time-sharing background suppression

作　　者：周杨帆[1] 谢亮[1] 夏晓娟[1] 孙伟锋[1] 

机构地区：[1]东南大学国家专用集成电路系统工程技术研究中心,江苏南京210096

出　　处：《激光与红外》2009年第11期1219-1222,共4页Laser & Infrared

摘　　要：介绍了一种具有分时背景抑制功能的单元电路,该单元电路适合于大规模2D红外焦平面阵列。在减电流电路设计中,自级联管采用长沟道设计,工作在强反型区,各单元电路的减去电流不易受到工艺偏差的影响,有效地降低了具有分时背景抑制功能的单元电路间的背景抑制非均匀性(BSUN)。在背景电流为100 nA,积分时间为2.7 ms,减去电流为3.28μA,构成自级联管的两个晶体管阈值电压的最大失配均为10 mV时,具有分时背景抑制功能的单元电路间的BSNU为3.310%。A pixel readout circuit with time-sharing background suppression has been introduced for 2D infrared focal plane array in this paper. In the design of subtracted current circuit, the self-cascode transistors are designed in long channel and works in their strong inversion mode, making the subtracted current insensitive to variations in process. This can effectively reduce the background suppression non-uniformity （BSNU） of pixel-to-pixel readout circuits. With 100 nA background current,3.28 μA subtracted current,2.7 ms integration time, and 10 mV threshold voltage mismatch of self-cascode transistors, the BSNU can be as low as 3. 310%.

关 键 词：背景抑制 背景电流 读出电路 红外焦平面阵列 

分 类 号：TN215[电子电信—物理电子学]