电阻抗成像中高速高精度数字相敏检波器设计  

High-speed,high-precision digital phase-sensitive detector design for electrical impedance tomography

作　　者：何为[1] 何传红[1] 刘斌[1] 

机构地区：[1]重庆大学输配电装备及系统安全与新技术国家重点实验室,重庆400030

出　　处：《重庆大学学报（自然科学版）》2009年第11期1274-1279,1290,共7页Journal of Chongqing University

基　　金：国家高技术研究发展计划(863计划)资助项目(2006AA02Z4B7);中俄国际合作项目(ISCP2007DFR30080)

摘　　要：电阻抗成像对测量系统的精度和速度都有较高要求,为此研制了基于现场可编程门阵列(field programmable gate array,FPGA)的数字相敏检波器(digital phase-sensitive detector,DPSD)用于电阻抗成像的数据测量。在分析DPSD原理的基础上,推导出信噪比与采样点数和采样分辨率的关系。给出了测量系统的实现方案,提出了基于直接数字频率合成(direct digitalsynthesis,DDS)技术的模数转换器(analog-to-digital converter,ADC)时钟设计方法。采用高速多通道ADC芯片,辅以低抖动ADC时钟电路,最终由FPGA实现实时DPSD算法。实验测试结果显示,测量准确度可达0.03%,系统信噪比可达85dB。琼脂模型成像实验证明其性能可以较好地满足电阻抗成像的要求。Electrical impedance tomography （EIT） system must have the properties of high precision and speed, thus the digital phase-sensitive detector （DPSD） based on the field programmable gate array （FPGA） is developed for data collection of EIT. Based on the principle of DPSD, the relationship between signal-to-noise ratio （SNR） and sample resolution as well as total number of samples is deduced. An implementation scheme of this system and a method of designing analog-to-digital converter （ADC） clock based on direct digital synthesis （DDS） technology are provided. The system adopts high-speed multichannel ADC and low jitter clock conditioner for ADC. Real-time DPSD is implemented with FPGA. The experiments show that the measurement accuracy reaches 0.03% and the SNR reaches 85 dB. The agar phantom experiments prove that the performance of the DPSD meet the designing requirement for EIT.

关 键 词：电阻抗成像 数字相敏检波器 信噪比 现场可编程门阵列 

分 类 号：TM930[电气工程—电力电子与电力传动]