单双精度浮点除法器的实现  

The Realization of Single-double Floating-point Division

作　　者：王晨旭[1] 朱世林[1] 王新胜[1] 

机构地区：[1]哈尔滨工业大学威海微电子中,威海264209

出　　处：《微处理机》2009年第5期20-23,共4页Microprocessors

摘　　要：通过对除法算法的研究,采用三级流水并精选SRT的冗余区域,在不减少运算精度的条件下,简化硬件设计,用硬件描述语言(Verilog)实现了单精度和双精度浮点数除法运算模块,并使用随机测试矢量对除法器进行验证,结果与参考机比较误差不超过2-64。如果采用SMIC0.18μmCMOS工艺库实现该设计,该除法单元在占用芯片面积为168173μm2的情况下工作频率可达约455MHz。Studying the division arithmetic,introduce 3-stage pipeline and select the SRT s redundancy area carefully in order to ease the design of hardware without reducing the precision.It realizes the division arithmetic of single-double floating-point using Verilog HDL,and verifies the design by using random stimulus.Compared with reference result,the difference is less than 2-64.If the design is implemented with SMIC 0.18μm CMOS processs,the working frequency can be up to 455MHz with consuming only 168173μm2 chip area.

关 键 词：三级流水 SRT算法 单双精度 浮点处理器 

分 类 号：TN4[电子电信—微电子学与固体电子学]