数字示波表中超高速数据采集系统的设计  

Design of Ultra High Speed Data Acquisition System in Digital Oscillometer

作　　者：渠海青[1] 孙艳萍[1] 朱正伟[1] 

机构地区：[1]江苏工业学院信息科学与工程学院,江苏常州213164

出　　处：《自动化仪表》2009年第11期67-69,73,共4页Process Automation Instrumentation

摘　　要：针对数字示波表的数据采集系统接口复杂、采集速度高、单片机难以实现等特点,介绍了一种以CPLD为核心的超高速数据采集系统设计方案。该方案采用高速A/D转换器、双片高速FIFO芯片来实现数字示波表中信号的不间断采样和存储,利用等精度测频技术自动生成FIFO的写入时钟,实现滤除冗余数据的功能。分别对A/D转换器、FIFO存储器、数据处理单元之间的逻辑接口电路以及测频原理、分频算法等进行了详细介绍。仿真结果表明,该设计完全满足数据采集系统的要求。Aiming at the features of data acquisition system of digital oscillometer, i.e. complex interface, high-speed collection, and difficult to be implemented with single chip computer, a design scheme for ultra high speed data acquisition system with CPLD as the core is introduced. In the design, the signals of digital oscillometer are uninterrupted sampled and stored by adopting high speed A/D converter and high speed dual FIFO chips ; the write-in clock of the FIFO is generated automatically with the technology of equivalent precision frequency measurement, for fil- tering the redundant data. The logical interfacing circuits among A/D converter, FIFO memory, and data processing unit, as well as the frequency measuring principle and algorithm of dividing frequency are respectively introduced in detail. The result of simulation shows that the design entirely meets the requirement of data acquisition system.

关 键 词：数字示波表 超高速数据采集 分频算法 CPLD接口电路 FIFO 

分 类 号：TP274.2[自动化与计算机技术—检测技术与自动化装置]