基于FPGA的雷达数字接收机设计与实现  

Design and Implementation of a Digital Radar Receiver Based on FPGA

作　　者：冯振伟[1,2] 武小冬 游思理 梅顺良[1] 

机构地区：[1]清华大学电子工程系,北京100084 [2]北京雷音电子技术开发有限公司,北京100070

出　　处：《现代雷达》2009年第11期72-76,共5页Modern Radar

摘　　要：现代雷达系统对接收机提出了更高的要求,数字接收机技术是实现高精度宽带雷达接收系统的一种有效途径。文中研究了数字接收机的相关理论和技术,介绍了数字下变频,数控振荡器、级联积分梳状滤波器和抽取。给出了一种基于FPGA的数字接收机实现方案,进行了分析和仿真,给出了测试结果。Higher performance is required for a receiver of modern radar system. Digital receiver technology is an effective implementation method of high accuracy and wide band radar receiving systems. The theory and technology of digital receiver are introduced in this paper. The digital down conversion, Number Controlled Oscillator （NCO） , Cascade integrator comb （ CIC ） filter and decimation are discussed. An example for implementing a digital receiver based on FPGA is presented. The analysis and simulation are made and the test results are provided.

关 键 词：数字接收机 现场可编程门阵列 数字下变频 数控振荡器 级联积分梳状滤波器 

分 类 号：TN957.5[电子电信—信号与信息处理]