基于Altera FPGA的部分串行FIR滤波器  

Partly serial FIR filter based on Altera FPGA

作　　者：郭雨梅[1] 陈曦[1] 

机构地区：[1]沈阳工业大学信息科学与工程学院,沈阳110870

出　　处：《沈阳工业大学学报》2009年第5期577-581,共5页Journal of Shenyang University of Technology

基　　金：辽宁省自然科学基金资助项目(20062043);辽宁省科技攻关资助项目(2006219005);辽宁省教育厅科研资助项目(20060629);沈阳市科技局科技支撑计划支持项目(1081229-1-00)

摘　　要：为了设计资源消耗少、性能优良、通用性强的FIR滤波器,提出一种利用Altera CYCLONEIII系列FPGA内部M9KRAM、硬件乘法器和逻辑单元构建部分串行FIR滤波器的设计思想.与完全串行结构相比,成倍提高了运算速度,减少了运算延迟;与完全并行结构相比,减少了逻辑单元的消耗.利用MATLAB中的fdatool工具设计FIR滤波器,并对系数进行量化;利用Quartus软件编译,并通过Modelsim软件仿真testbench中响应的输入、输出量.仿真结果验证了该设计方法的正确性,所设计的部分串行FIR滤波器具有资源消耗少、运算速度快等特点.To design the FIR filter with the less resource consumption, excellent performance and high universality, a design method to construct the partly serial FIR filter using M9K RAM of Altera CYCLONEⅢ serial FPGA, embedded multipliers and logic cells was proposed. Compared with the fully serial structure, the present structure increases the operation speed, decreases the operation delay and consumes less logic cells. With using the fdatool in MATLAB, the FIR filter was designed, and the coefficients was quantized. By compiling with Quartus software, the input and output of the response in testbench were simulated using Modelsim software. The simulation results prove the correctness of the present method. The designed partly serial FIR filter has such characteristics as less resource consumes and larger operation speed.

关 键 词：现场可编程逻辑阵列 FIR滤波器 部分串行 fdatool工具 M9KRAM模块 硬件乘法器 Modelsim仿真 低延迟 

分 类 号：TN713[电子电信—电路与系统]