一种图像缩放的简化双线性插值电路  

Simplify Circuit of Linear Interpolation for Image Zoom

作　　者：廖汝鹏[1] 蔡泽锋[1] 闾晓晨[1] 郑学仁[1] 

机构地区：[1]华南理工大学电子与信息学院微电子研究所,广东广州510640

出　　处：《微电子学与计算机》2009年第12期136-138,共3页Microelectronics & Computer

摘　　要：设计了一个新颖的图像缩放的线性插值电路.该电路只使用一个有符号的乘法器,与常用的滤波器形式插值电路相比,不需要额外的步长查找表地址产生器和ROM等电路,大大节省硬件开销.仿真结果表明:该电路正确完成线性插值运算,适用于双线性插值运算.A new circuit of linear interpolation is designed for the image expansion. A signed multiplier is used in this design. Compared with the interpolation circuit in common use using filter, it does not require extra address generator and ROM so as to cut down the cost of hardware. Ii is implied form the result of simulate for the designed circuit that it does the correct work of linear interpolation.

关 键 词：双线性插值 定标器 图像缩放 

分 类 号：TN949[电子电信—信号与信息处理]