基于FPGA的双DDS任意波发生器设计与杂散噪声抑制方法  

Design of dual DDS arbitrary wave generator based on FPGA and denoising of spur noise

作　　者：邓耀华[1,2] 吴黎明[1] 张力锴[1] 李业华[1] 

机构地区：[1]广东工业大学信息工程学院,广州510006 [2]华南理工大学机械与汽车工程学院,广州510643

出　　处：《仪器仪表学报》2009年第11期2255-2261,共7页Chinese Journal of Scientific Instrument

基　　金：广东省科技计划攻关项目(2004A10403008);广州市科技攻关重点项目(2007Z2-D3161)资助

摘　　要：研究基于DDS(直接数字频率合成)的任意波信号产生的机理,在FPGA内嵌SOPC,配置了32位的软微处理器NiosII,利用FPGA实现双DDS的相位累加器,通过数字方法直接实现任意波形的各种频率调制。分析了高速相位累加器截断误差,幅度量化误差和D/A非线性引起的杂散分量产生的原因。推导出DDS相位噪声模型,针对信号的频谱成份设计了高阶低通滤波器对输出信号滤波。结合NiosII,设计硬件电路对输出信号进行幅频校正,保证了信号幅值的稳定输出及实际显示数值的一致性。测试表明,信号波形发生器能输出稳定、高带宽、高速度、高精度、低衰减的任意波形,三角波的输出频率大于1MHz,输出信号幅度峰峰值在50mV～20V范围内以10mV的步进调节。In this paper, the principle of arbitrary wave generator based on DDS is studied; one 32-bit NioslI soft-core is embedded in an FPGA. Dual DDS phase accumulator is designed, through digital method different frequency modulations of arbitrary wave are implemented. The errors caused by phase truncation, amplitude quantization and nonlinear properties of D/A are analyzed, and then a phase noise model is deduced, a high-order low pass filter is designed according to the signal frequency spectrum. Combined with NiosII, a hardware correction circuit is designed to adjust the amplitude in different frequency bands, which guarantees the amplitude out- put and the consistency between the amplitude output and the displayed value in LCD. Final test shows that the wave generator can produce stable, high bandwidth, high speed, high precision and low attenuation arbitrary waves. The frequency of triangular wave is above I MHz, and the peak-peak amplitude of the output signal can be adjusted in a range from 50 mV to 20 V with a minimum step of 10 mV.

关 键 词：任意波发生器 SOPC 双DDS 相位截断 高阶滤波器 幅频校正 

分 类 号：TN911[电子电信—通信与信息系统]