基于FPGA的USB接口IP核设计  

Design of the USB Interface IP Core Base on FPGA

作　　者：姚成宇[1] 唐宁[1] 汪洋[1] 

机构地区：[1]桂林电子科技大学信息与通信学院,广西桂林541004

出　　处：《电子科技》2009年第12期34-37,共4页Electronic Science and Technology

摘　　要：重点阐述了USB接口IP核关键模块的设计和验证,用VerilogHDL对USB IP核协议RTL级代码编写,对USB协议的数据流、传输等进行了深入的分析,在Xilinx ISE软件平台上进行了FPGA综合,并在Xilinx FPGA开发板上调试成功。通过在ModelSim6.0上仿真、ISE9.1上综合并在FPGA开发板上验证,最后采用0.35μm CMOS工艺实现版图设计,工作频率120MHz,3.3V电压时工作电流9mA,静态电流40μA。结果表明文中USB接口IP设计是可行的。The design and verification of USB IP core key modules are discussed in detail. Modules of USB protocol layer controller RTL code are designed using VerilogHDL. Data streams and the transport are analyzed in detail, synthesized on the ISE platform of XILINX and verified by XILINX FPGA Sample Pack with success. The layout of the modules is fabricated by the 0. 35 μm CMOS process, which runs at 120 MHz frequency with an active supply current of 9 mA at 3.3 V supply, and a static current of 40 μA. Simulation results show that this IP design of USB interface is feasible.

关 键 词：IP 通用串行总线 VERILOGHDL 协议层 SIE 

分 类 号：TP334.7[自动化与计算机技术—计算机系统结构]