基于ADC的TR-UWB数字接收机性能及其FPGA实现  

Performance of TR-UWB Digital Receiver Based on A/D Conversion and Its Implementation on FPGA

作　　者：许燕[1] 许洪光[1] 

机构地区：[1]哈尔滨工业大学深圳研究生院,深圳518055

出　　处：《数据采集与处理》2009年第B10期74-78,共5页Journal of Data Acquisition and Processing

基　　金：国家自然科学基金(50323005)资助项目

摘　　要：发送参考超宽带(Transmitled reference UWB,TR-UWB)系统采用自相关接收检测技术作为一种非最优接收机,不需要进行信道估计和精确的时间同步,其结构简单、性能优良。数字化TR自相关接收机可以充分利用数字信号处理算法的优势,且易于用集成电路方法实现,其实现的关键是ADC。本文从理论上分析了ADC的抽样速率、量化阶数等对数字接收机的性能的影响,提出了过高阶数的量化并不能有效改善系统性能,并在FPGA上实现了TR-UWB接收机,通过编程设计与仿真,验证了基于ADC的TR-UWB接收机实现的可行性。TR-UWB system uses an autocorrelation detection as a suboptimal receiver, it is no need to do channel estimation and exact time synchronization. The implementation is simple and its performance is good. Digitalized TR autoeorrelation receiver can use the current digital signal processing technology to be realized by the integrated circuit easily. During the imple- mentation, ADC performance is one of the key factors to be considerer. This paper analyzes the effects of the sampling rate and the quantitative order to the digital receiver theoretically. And it is proposed that high quantization order cannot improve the system function. Finally, a TR-UWB digital receiver is implemented based on FPGA. By programming design and simulation, it is concluded that TR-UWB digital receiver based on ADC can be achieved.

关 键 词：传输参考超宽带 模/数转换器 抽样速率 量化阶数 FPGA 

分 类 号：TN914.2[电子电信—通信与信息系统]