单片UHF RFID阅读器中低噪声频率综合器的设计  

A Low Phase Noise Frequency Synthesizer for Single-Chip UHF RFID Reader

作　　者：何伟[1] 张润曦[2] 徐萍[1] 张勇[1] 陈子晏[1] 赖宗声[1,3] 

机构地区：[1]华东师范大学微电子电路与系统研究所,上海200062 [2]苏州职业大学,江苏苏州215000 [3]华东师范大学纳光电集成与先进装备教育部工程研究中心,上海200062

出　　处：《微电子学》2009年第6期733-737,共5页Microelectronics

基　　金：上海AM基金资助项目(07SA04);上海重点学科建设项目(B411)

摘　　要：结合EPC global C1 G2协议和ETSI规范要求,讨论了频率综合器噪声性能需求,并设计实现了用于单片CMOS UHF RFID阅读器中的低噪声三阶电荷泵锁相环频率综合器。在关键模块LC VCO的设计中,采用对称LC滤波器和LDO调节器提高VCO相位噪声性能。电路采用IBM 0.18μm CMOS RF工艺实现,测得频率综合器在中心频率频偏200 kHz和1 MHz处相位噪声分别为-109.13 dBc/Hz和-127.02 dBc/Hz。Requirements of frequency synthesizer on phase noise were discussed based on EPC global C1G2 and ETSI multi-protocol operation. A low phase noise 3rd-order II-type charge pump phase locked loop for single-chip CMOS UHF RFID reader was presented, which acted as a frequency synthesizer. Symmetrical LC filters and LDO regulator were used to improve phase noise performance. The circuit was implemented in 0. 18μm CMOS RF technology. Test results showed that the frequency synthesizer had a phase noise of -109. 13 dBc/Hz and -127. 02 dBc/ Hz, at 200 kHz and 1 MHz offset from the carrier, respectively.

关 键 词：CMOS 超高频射频识别 频率综合器 相位噪声 

分 类 号：TN431.1[电子电信—微电子学与固体电子学]