高性能SRAM的低功耗设计  

Low-Power Design of High-Performance SRAM

作　　者：熊凯[1] 谭全林[1] 邢座程[1] 李少青[1] 

机构地区：[1]国防科技大学计算机学院,长沙410073

出　　处：《微电子学》2009年第6期760-764,共5页Microelectronics

基　　金：国家高技术研究发展(863)计划基金资助项目(2007AA01Z102)

摘　　要：采用0.13μm标准CMOS工艺,全定制设计实现了一款8 kB(8 k*8 bit)的高速低功耗静态随机存取存储器(SRAM)。分析了影响存储器性能和功耗的原因,并在电路布局上做了改进,将两个3-8译码器进行拆分与重组,降低了互连线的延迟和耦合作用;同时,对灵敏放大器也做了改进。版图后仿真表明,在电源电压为1.2 V、温度为25℃的典型条件下,读1延时为766.37 ps,最大功耗为11.29 mW,功耗延时积PDP为8.65 pJ,实现了很好的性能。A fully customized high-speed and low-power 8 kB SRAM was designed and implemented using 0. 13 μm standard CMOS process. Factors affecting performance and power of SRAM were analyzed. And the circuit layout was improved. By splitting and regrouping two 3-8 decoders, the delay and coupling of interconnected wire were shortened and improved, as well as sense-amplifier. Results from post-layout simulation showed that, at 1.2 V supply and 25℃, the circuit has a read-one delay of 766.37 ps, a maximum power of 11.29 mW, and a power-delay product （PDP） of 8.65 pJ.

关 键 词：SRAM 灵敏放大器 预充电路 译码电路 功耗延时积 

分 类 号：TN432[电子电信—微电子学与固体电子学]