2.45 GHz 0.18μm全差分CMOS低噪声放大器设计  

Design of 2.45 GHz Fully Differentially Low Noise Amplifier in 0.18μm CMOS Technology

作　　者：齐凯[1] 蔡理[1] 

机构地区：[1]空军工程大学理学院,西安710051

出　　处：《微电子学》2009年第6期773-777,共5页Microelectronics

摘　　要：设计了一个基于TSMC 0.18μm CMOS工艺的2.45 GHz全差分CMOS低噪声放大器。根据电路结构特点,采用图解法对LNA进行功耗约束下的噪声优化,以选取最优的晶体管栅宽;设计了仅消耗15μA电流的偏置电路;采用在输入级增加电容的方法,在改善输入匹配网络特性的同时,解决了栅极电感的集成问题。仿真结果表明:LNA噪声系数为1.96 dB,功率增益S21超过20 dB,输入反射系数S11和输出反射系数S22分别小于-30 dB和-20 dB,反向功率增益S12小于-30 dB,1 dB压缩点和三阶互调输入点IIP3分别达到-17.1 dBm和-2.55 dBm,整个电路在1.8V电源下功耗为22.4 mW。A 2.45 GHz fully differential low noise amplifier （LNA） was designed based on TSMC＇s 0. 18 μm CMOS technology. Based on LNA topology, noise optimization was done at given power dissipation by using graphic method, to choose the optimal transistor width. A bias circuit consuming only 15 μA of current was designed＇ in which input-matching performance was improved and the problem of gate inductance integration was solved by adding a capacitor to input stage of the I.NA. Simulation results showed that the resulting LNA had a noise figure of 1.96 dB, a power gain （S21） of 20.1 dB, an input reflectivity Sn and output reflectivity S22 less than -30 dB and -20 dB, respectively, a reversed power gain S12 better than -30 dB; and a P1dB of -17. 1 dBm and an IIP3 of -2.55 dBm, respectively. The circuit consumes 22. 4 mW of power from a 1.8 V supply.

关 键 词：低噪声放大器 噪声优化 输入匹配 偏置电路 

分 类 号：TN772.3[电子电信—电路与系统]