稳定占空比高速SSTL_2 I/O缓冲器的实现  

Design of SSTL_2 Standard I/O Buffers with Stable Duty Cycle

作　　者：屈小钢[1,2] 杨海钢[1] 孙嘉斌[1,2] 韦援丰[1] 

机构地区：[1]中国科学院电子学研究所,北京100190 [2]中国科学院研究生院,北京100049

出　　处：《微电子学》2009年第6期778-781,785,共5页Microelectronics

摘　　要：应对时钟上升沿和下降沿均采集数据的芯片间高速接口,提出了一种输出占空比在50%左右、偏差范围±5%的支持SSTL_2标准的I/O缓冲器。利用互补有源电流镜差动对,实现在不同温度和工艺角下输出信号稳定的占空比偏差范围的输入接收器。为了验证电路实际工作性能,测试芯片在SMIC 0.18μm 1P6M混合信号工艺下流片。测试结果显示,333 MHz时,输出占空比为47%;200 MHz时,输出占空比为48%;与已报道的支持SSTL_2标准的接收器相比,工作在333 MHz时,输出占空比仍保持在45%到55%间,偏差范围减小约72%。In view of high speed interfaces which samples on condition of both rising and falling edges, an SSTL_2 standard-supported I/O buffer was proposed, which featured a duty cycle of around 50% and a deviation range of ± 5%. Utilizing complementary differential pairs of current-mirror loads, an input receiver with invariable deviation range of duty cycle was implemented at different temperatures and process corners. Test chip was designed and fab- ricated in SMIC＇s 0. 18 μm 1P6M mixed signal process. Test results showed that the circuit had a duty cycle of 47% at 333 MHz and 48% at 200 MHz, respectively. Compared with existing SSTL-2 standard receiver, deviation of output duty cycle was reduced by 72% for operation at 333 MHz.

关 键 词：I/O缓冲器 SSTL_2标准 占空比 

分 类 号：TN402[电子电信—微电子学与固体电子学]