新型电流型CMOS四值边沿触发器设计  

Novel current-mode CMOS quaternary edge-triggered flip-flops

作　　者：杭国强[1] 应时彦[2] 

机构地区：[1]浙江大学信息与通信工程研究所,浙江省综合信息网技术重点实验室,浙江杭州310027 [2]浙江工业大学信息工程学院,浙江杭州310014

出　　处：《浙江大学学报（工学版）》2009年第11期1970-1974,共5页Journal of Zhejiang University：Engineering Science

基　　金：国家自然科学基金资助项目(60971061);浙江省自然科学基金资助项目(Y105124,Y106375)

摘　　要：提出3种应用于多值逻辑系统的电流型触发器设计,包括四值主从结构触发器、单闩锁单边沿触发器和单闩锁双边沿触发器.采用电流阈值控制技术简化这些电路的结构.单个锁存器的四值单边沿和双边沿触发器分别利用时钟信号的1个边沿和2个边沿后产生的窄脉冲使锁存器瞬时导通,实现取样求值.单闩锁结构的触发器不仅可以简化电路结构,更重要的是大大降低了电流型触发器的直流功耗.在保持相同数据吞吐量的条件下,应用双边沿触发器可以使时钟信号的频率减半,从而降低时钟网络的动态功耗.采用TSMC 0.25μm CMOS工艺参数的HSPICE模拟结果验证了所提出设计方案的有效性.Three new current-mode CMOS flip-flops applied to multiple-valued logic （MVL） systems were presented, including quaternary master-slave flip-flop, one-latch quaternary single edge-triggered （1L-QSET） flip-flop and one-latch quaternary double edge-triggered flip-flop （1L-QDET）. The constructions of the circuits were simplified by employing the current threshold-controlling technique. In the 1L-QSET and 1L-QDET configurations, data are sampled into the latch during a transparency period for one edge or each edge of the clock signal, respectively. In comparison with the current-mode quaternary master-slave flip-flop, the one-latch configurations reduce the transistor count and lower the static power consumption. For a given throughput, the clock frequency can be halved using the double edged-triggered flip-flops, therefore the dynamic power dissipation of the clock network can be reduced. The HSPICE simulation using TSMC 0.25 μm CMOS technology validated the effectiveness of the proposed approach. Finally, the simulated results of the propagation delay and the power dissipation were compared among the proposed quaternary flip-flops.

关 键 词：电流型CMOS 多值逻辑 触发器 低功耗设计 

分 类 号：TN432[电子电信—微电子学与固体电子学]