一种有效降低扫描结构测试功耗的方法  

An Effective Method for Depressing Scan-based Test Power

作　　者：张红南[1] 王松[1,2] 徐君[2] 李向库[2] 张志伟[1] 

机构地区：[1]湖南大学物理与微电子科学学院,湖南长沙410082 [2]中国科学院计算技术研究所,北京100190

出　　处：《湖南大学学报（自然科学版）》2009年第12期45-48,共4页Journal of Hunan University:Natural Sciences

基　　金：湖南省自然科学基金资助项目(851204013)

摘　　要：提出了一种有效降低扫描测试功耗的设计方案.通过增加逻辑门结构来控制测试向量移入阶段扫描链上触发器翻转向组合逻辑电路的传播.同时,设计了时序优化算法以保持电路其他性能不发生大的改变.实验结果显示:通过采用ISCAS89基准测试程序进行分析,优化前无用动态功耗值约占总功耗的19.84%,优化后整体测试功耗降低约23%,有效地降低了无用动态功耗,并且此方案容易在已有的设计流程里实现.The scan-based testing method is often used to solve the problems of testing sequential logic, and its application is limited for the high-power operation characteristics. This paper proposed an effective scheme to reduce the scan-based test power to prevent the transitions of scan chains from reflecting into the combinational logic circuit lines by adding some logic gates. Then, we introduced an optimizational arithmetic ensuring other performances of the chip. The experiment results of ISCAS89 benchmark have shown that the useless dynamic power consumption accounts for about 19.84% of the total power consumption, while the overall test power consumption has been reduced by approximately 23 % after optimization. This mechanism effectively reduces the unwanted dynamics power consumption, and it is easier to implement by means of the existing methods.

关 键 词：扫描测试 测试向量 组合逻辑电路 动态功耗 

分 类 号：TN407[电子电信—微电子学与固体电子学]