QPSK全数字接收机定时同步环路  

Timing Synchronization Loop for QPSL All Digital Receiver

作　　者：马晶[1] 周冲[1] 晏辉[1] 

机构地区：[1]电子科技大学通信抗干扰技术国家级重点实验室,四川成都610054

出　　处：《通信技术》2009年第12期4-6,共3页Communications Technology

基　　金：国家基金863计划(编号:2006AA01Z269)

摘　　要：将三阶立方拉格朗日多项式内插算法和Gardner定时误差检测算法应用于QPSK全数字接收机定时同步环路,并对构成环路的其他部分,环路滤波器以及数控振荡器进行分析并提出实现方法。通过仿真,证明上述算法具有良好的性能,可以很好的解决定时同步问题,并在FPGA上实现整个环路设计方案,使得数字解调的硬件实现具有良好的灵活性和可移植性。This paper proposes a scheme of timing synchronization loop for QPSK all digital receiver. The cubic Lagrange polynomial interpolation algorithm and Gardner s algorithm of timing error detector,are utilized,and other parts of the timing synchronization loop--loop filter and numerical control oscillator are analyzed. The methods of implementation are also given in this paper. Simulation results indicate that the SER performance of Lagrange interpolation algorithm is excellent,and the proposed scheme is a good solution for timing synchronization. The loop design is implemented on FPGA, and a flexible and portable method for hardware implementation of digital demodulation is provided.

关 键 词：定时同步 内插滤波器 定时误差检测算法 

分 类 号：TN911.8[电子电信—通信与信息系统]