DVB系统中扰码发生器的FPGA实现  

FPGA Implementation of Pseudo-random Generator in DVB System

作　　者：吕锋[1] 徐宇白[1] 

机构地区：[1]武汉理工大学信息学院通信试验室,湖北武汉430070

出　　处：《通信技术》2009年第12期188-190,共3页Communications Technology

基　　金：863计划(编号:2007AA12Z170)

摘　　要：为了保证在任何情况下进入数字电视DVB传输系统的数据码流中"0"与"1"的概率都能基本相等,传输系统首先要用一个伪随机序列对输入的MPEG-2码流进行扰乱处理。给出了DVB标准中扰码发生器的FPGA设计方案,并以Altera公司的QuartusII为开发平台,运用Verilog语言描述了各部分设计并给出仿真结果。In order to comply with the systems for digital television DVB standard and to equalize the rate of binary codes ＂0＂ and ＂1＂ for clock recovery,the data at the output of MPEG-2 transport is randomized by pseudo-random generator. This paper presents a design and implementation of pseudo-random generator for DVB standard based on FPGA,describes the random sequence described in Verilog and realized in QuartusII platform. And finally,the simulation results are given in this paper.

关 键 词：数字视频广播 扰码发生器 FPGA M序列 

分 类 号：TN919.3[电子电信—通信与信息系统]