S波段锁相频率合成器的设计  

On the Design of Synthesizer of S-band PLL Frequency

作　　者：王飞[1] 马胜前[1] 

机构地区：[1]西北师范大学物理与电子工程学院,甘肃兰州730070

出　　处：《安徽职业技术学院学报》2009年第4期16-19,共4页Journal of Anhui Vocational & Technical College

摘　　要：文章分析了频率合成器的设计方法,采用小数N锁相器ADF4153设计了S波段的频率合成器,输出频率范围为2.85GHz-3.35GHz的宽带频率信号,重点介绍了元器件的选择和环路滤波器的设计,并用ADIsimPLL软件进行环路滤波器的优化。同时,使用低介电常数的rogers板设计微带功分器,采用ADS对Wilkinson功分器进行仿真和优化,仿真和实验结果验证了电路的可行性。This paper analyzes the design method of frequency synthesizer, using fractional-N phase-locked ADF4153 to design S band frequency synthesizer whose frequency range is from 2. 85GHz to 3.35GHz. It mainly introduces the selection of key components and loop filter design and using of ADIsimPLL software to optimize the loop filter. Meanwhile, low dielectric constant rogers board design divider is used, Wilkinson power divider is optimized and simulated by using ADS, and the feasibility of the circuit is proved from the simulation and results.

关 键 词：ADF4153 锁相环 环路滤波器 功分器 

分 类 号：TM935.1[电气工程—电力电子与电力传动]