一种基于0.35m工艺的高速混合旋转结构DDFS  

A High-speed Direct Digital Frequency Synthesizer with Mixed-rotation Structure in 0.35 μm CMOS

作　　者：万书芹[1] 季惠才[2] 于宗光[1,2] 阮园[2] 陈珍海[2] 张凯虹[2] 

机构地区：[1]江南大学信息工程学院,江苏无锡214000 [2]中国电子科技集团公司第58研究所,江苏无锡214000

出　　处：《固体电子学研究与进展》2009年第4期505-510,共6页Research & Progress of SSE

基　　金：江苏省自然科学基金(BK2007026)

摘　　要：设计实现了一种基于CORDIC算法和乘法器的直接数字频率合成器。采用混合旋转算法实现相位幅度转换,最高工作频率达到400MHz。在算法级,将DDFS中需要执行的π/4旋转操作分成两次旋转完成,第一次旋转采用CORDIC算法,第二次旋转采用乘法器来完成,同时采用流水线结构来实现累加器,提高整体性能。在晶体管级,采用DPL(Double-pass-transistor logic)逻辑实现基本电路单元,减少延迟提高速度。经0.35μmCMOS工艺流片,在400MHz的工作频率下,输出信号在80MHz处,SFDR为76.47dB,整个芯片面积为3.4mm×3.8mm。This paper presents a novel implementation of a 400 MHz direct digital frequency synthesizer based on mixed-rotation architecture in 0. 35μm CMOS technology. At the algorith- mic level, the π/4 rotation operation required is divided into two steps. The first rotation is im- plemented by CORDIC algorithm and the second rotation is achieved by multiplier. The CORDIC algorithm is realized in pipeline and carry-save arithmetic. At the same time, the pipeline struc- ture is used to achieve an accumulator, so the overall performance is improved. At the transistor level, DPL（double-pass-transistor logic） is employed to implement basic unit and reduce the delay. The measured SFDR is 76.47 dB with an output frequency of 80 MHz at a clock frequency of 400 MHz. The DDFS is fabricated in 0, 35 μm N-well 2P3M CMOS process. The area of the chip is 3.4mm×3.8mm.

关 键 词：直接数字频率合成 CORDIC算法 流水线设计 角度旋转 

分 类 号：TN432[电子电信—微电子学与固体电子学]