Study of a SiGe-HBT-based 1:2 demultiplexer IC up to 100 Gb/s rate  

作　　者：胡正飞 

机构地区：[1]Institute of Science,Nanjing University of Posts and Telecommunications

出　　处：《Optoelectronics Letters》2010年第1期24-26,共3页光电子快报（英文版）

基　　金：supported by the Communication Systems Project of Jiangsu Education Department (No.JHB04010)

摘　　要：An ultra-high speed 1:2 demultiplexer for optical fiber communication systems is designed utilizing the IHP 0.25 μm SiGe BiCMOS technology. The latch of the demultiplexer core circuit is researched. Based on the current measurement condition, a high-gain and wide-bandwidth clock buffer is designed to drive large load. Transmission line theory for ultra-high speed circuits is used to design matching network to solve the matching problem among the input, output and internal signals. The transient analysis shows that this demultiplexer can demultiplex one 100 Gb/s input into two 50 Gb/s outputs. The chip area of it is 0.7 mm×0.47 mm, the input and output data are both at 400 mVP-P PCML standard voltage level, and the power consumption of the IC is 900 mW at the power supply of -4 V.An ultra-high speed 1：2 demultiplexer for optical fiber communication systems is designed utilizing the IHP 0.25 μm SiGe BiCMOS technology. The latch of the demultiplexer core circuit is researched. Based on the current measurement condition, a high-gain and wide-bandwidth clock buffer is designed to drive large load. Transmission line theory for ultra-high speed circuits is used to design matching network to solve the matching problem among the input, output and internal signals. The transient analysis shows that this demultiplexer can demultiplex one 100 Gb/s input into two 50 Gb/s outputs. The chip area of it is 0.7 mm×0.47 mm, the input and output data are both at 400 mVP-P PCML standard voltage level, and the power consumption of the IC is 900 mW at the power supply of -4 V.

关 键 词：集成电路 Gb 晶体管 BICMOS技术 信号分离器 超高速电路 分接 基础 

分 类 号：TN32[电子电信—物理电子学]