A 4224 MHz low jitter phase-locked loop in 0.13-μm CMOS technology  

作　　者：陈虎 陆波 邵轲 夏玲琍 黄煜梅 洪志良 

机构地区：[1]State Key Laboratory of ASIC & System,Fudan University

出　　处：《Journal of Semiconductors》2010年第1期46-50,共5页半导体学报（英文版）

基　　金：supported by the National High Technology Research and Development Program of China(No.SQ2008AA01Z4473469).

摘　　要：A 4224 MHz phase-locked loop （PLL） is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump. Dynamic mismatch of charge pump is considered. By balancing the switch signals of the charge pump, a good dynamic matching characteristic is achieved. A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance. The 4224 MHz PLL achieves phase noises of-94 dBc/Hz and -114.4 dBc/Hz at frequency offsets of 10 kHz and 1 MHz, respectively. The integrated RMS jitter of the PLL is 0.57 ps （100 Hz to 100 MHz） and the PLL has a reference spur of-63 dB with the second order passive low pass filter.A 4224 MHz phase-locked loop （PLL） is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump. Dynamic mismatch of charge pump is considered. By balancing the switch signals of the charge pump, a good dynamic matching characteristic is achieved. A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance. The 4224 MHz PLL achieves phase noises of-94 dBc/Hz and -114.4 dBc/Hz at frequency offsets of 10 kHz and 1 MHz, respectively. The integrated RMS jitter of the PLL is 0.57 ps （100 Hz to 100 MHz） and the PLL has a reference spur of-63 dB with the second order passive low pass filter.

关 键 词：PLL in-band noise dynamic mismatch RMS jitter 

分 类 号：TN432[电子电信—微电子学与固体电子学]