针对AES密码芯片的CPA攻击  

Study of CPA on AES chip

作　　者：樊海锋[1] 徐金甫[1] 严迎建[1] 

机构地区：[1]解放军信息工程大学电子技术学院,河南郑州450004

出　　处：《计算机工程与设计》2010年第1期37-40,共4页Computer Engineering and Design

摘　　要：为证明未加抗功耗分析措施的AES密码芯片容易受到相关性功耗分析威胁的事实,提出了针对AES密码芯片的相关性功耗分析(CPA)方法,并进行了CPA功耗分析攻击实验。通过提取AES密码算法硬件结构中的关键寄存器信息,利用适当的功耗模型将这些信息转换为模拟瞬时功耗信息,并与采用实际测量装置测量的功耗信息进行相关性分析实验。实验成功破解了AES密码芯片中的最高8比特密钥值。实验结果表明了未加防御措施的AES密码芯片面临CPA攻击时的脆弱性。To confirm the fact that AES chip without countermeasures is vulnerable to correlation power analysis （CPA）. A method of correlation power analysis to AES chip is proposed. A correlation power analysis experiment is mounted on AES chip. With extracting critical register＇ s information from AES hardware architecture and adopting proper power model,this information is converted to simulated instantaneous power. The simulated instantaneous power data is correlated with the power data measured from practical measurement. Eight most significant bits of key are obtained from the experiment. The result of the experiment reveals the vulnerability of AES chip without countermeasures to CPA attack.

关 键 词：高级加密标准 相关性功耗分析 密码芯片 相关系数 防御措施 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]