全流水线结构双精度浮点乘加单元的设计  

Design of a Fully Pipelined Double-Precision Multiply-Add-Fused Unit

作　　者：蔡敏[1] 闵言灿[1] 

机构地区：[1]华南理工大学电信学院,广东广州510641

出　　处：《微电子学与计算机》2010年第1期53-56,60,共5页Microelectronics & Computer

基　　金："十一五"微电子预研项目

摘　　要：提出了一种支持非规格化数的全流水线结构双精度浮点乘加单元(Multiply-Add-Fused Unit,MAF,A×C+B).该乘加单元并行处理了主加法和舍入操作,解决了进位保存形式的乘法结果带来的一位误差,改进了规格化移位以便于流水线的划分.整个乘加单元划分为三级流水线,在0.13μm CMOS标准单元库中,综合结果支持333 MHz的时钟频率.This paper presents a fully pipetined double precision MAF（ Multiply Add Fused unit, A × C ＋ B）, which accepts denormalized numbers. The unit is based on combination of the rounding with final addition, moreover, a method to deal with the one bit error from the carry saved format of multiply result is proposed, finally, the rounding architecture is improved for getting better pipeline structure. The overall MAF has a latency of 3 cycles a throughput of 1 cycle, and a frequency of 333MHz in 0.13μm CMOS technology.

关 键 词：乘加单元 流水线 非规格化数 

分 类 号：TN4[电子电信—微电子学与固体电子学]