超宽带系统CMOS全集成射频收发器设计  

作　　者：郑仁亮[1] 杨光[1] 江旭东[1] 姚望[1] 尹江伟[1] 郑剑钦[1] 李巍[1] 李宁[1] 任俊彦[1] 

机构地区：[1]复旦大学专用集成电路与系统国际重点实验室,上海201203

出　　处：《中国集成电路》2010年第1期32-38,共7页China lntegrated Circuit

基　　金：上海市科委集成电路设计专项(08706200700)

摘　　要：本文介绍3.1-4.8GHz MB-OFDM系统的CMOS射频收发器。电路采用直接变频架构,由接收器、发射器和频率综合器组成。采用PGS隔离技术和其他隔离措施完成了单片射频收发器的版图布局。后仿真结果表明,接收链路可提供的最大增益为72dB,其52dB为可变增益,三个子频带内噪声系数介于5.2-7.8dB,带外IIP3不低于-3.4dBm。发射链路可提供的可控输出功率-8dBm到-2dBm,输出1dB压缩点不低于4dBm,输出信号边带抑制约44dBc,载波抑制不低于34dBc。频率综合器在三个频点间的跳变时间小于9ns。芯片采用Jazz0.18μm射频CMOS工艺设计,面积为6.1mm2。在1.8V电源电压下,总电流约221mA。A fully integrated transceiver for WiMedia MB-OFDMUWB system in the 3.1-4.8GHz band is present in this paper.The transceiver adopts direct-conversion architecture including RF Receiver,Transmitter and Synthesizer.The post simulation results show that the receiver achieves a maximum total voltage gain of 72dB with AGC range of 52dB,an average total noise figure of 5.2 to 7.8dB in the three bands and the outband IIP3 better than -3.4dBm.The transmitter achieves an controllable output power between -8 to -2dBm,the output P1dB better than 4dBm and the sideband rejection about 44dBc and the LO suppression of 34dBc.The switching time between different bands is less than 9ns.The ESD protected chip is fabricated in Jazz 0.18μm RF CMOS process with an area of 6.1mm2,consuming about 221mA（RX＋TX＋Syn＋Buffers）from 1.8V supply.

关 键 词：超宽带 射频收发器 接收器 发射器 频率综合器 

分 类 号：TN859[电子电信—信息与通信工程] TN432