基于寄存器组的FFT处理器  

Register group based FFT processor

作　　者：蔡梦[1] 张科峰[1] 邹雪城[1] 杨晓峰[1] 

机构地区：[1]华中科技大学电子科学与技术系,湖北武汉430074

出　　处：《华中科技大学学报（自然科学版）》2010年第1期55-57,68,共4页Journal of Huazhong University of Science and Technology(Natural Science Edition)

基　　金：国家高技术研究发展计划资助项目(2006AA01Z226)

摘　　要：针对目前快速傅里叶变换(FFT)处理器存储器访问算法复杂度较高,实现起来面积较大的问题,采用寄存器交换策略实现无冲突地址读写.以存储器迭代结构为主体构建FFT处理器结构,并设计了一种基于流水线的蝶形运算单元.根据基4蝶形运算数据选择的规律性,采用数据移位操作可以去除存储器中的地址解码器和控制逻辑.采用门控时钟降低系统的功耗.设计的FFT处理器通过SMIC 0.18μm工艺综合仿真,其面积为0.6 mm2,整个处理过程只需要60个时钟周期.在20 MHz的工作频率下,系统的平均动态功耗为7mW.该结构可以满足IEEE 802.11a的要求,并且具有小面积及高效的特点.At present, the access scheme for fast Fourier transform （FFT） processors is very complicated and requires more areas of silicon for implicating of it. Thus, a register shift operation strategy was studied to deal with the problem. From the memory-based recursive structure, a small area and high efficiency FFT processor was proposed. Then a pipeline butterfly unit was found. According to the rule of radix-4 butterfly operation, the decoder and controller were replaced by data shift operations to reduce the hardware resources of the processor. Moreover, a clock-gating scheme was adopted to reduce the power consumption effectively. The processor was synthesized in SMIC 0. 18 μm technology. It occupies 0.61 mm^2 , and needs 60 clock cycles to complete the 64 points FFT computation. The average dynamic power consumption is 7 mW at 20 MHz operating frequency. The evaluation results show that the proposed method can meet the requirements of IEEE 802. lla, and has the advantages of low cost and high efficiency.

关 键 词：处理器 正交频分复用 快速傅里叶变换 存储器迭代 蝶形运算单元 无线局域网 

分 类 号：TN911.72[电子电信—通信与信息系统]