基于LBDL逻辑的抗DPA攻击电路设计方法  

An LBDL Based VLSI Design Method to Counteract DPA Attacks

作　　者：乐大珩[1] 李少青[1] 张民选[1] 

机构地区：[1]国防科技大学并行与分布处理国防科技重点实验室,湖南长沙410073

出　　处：《国防科技大学学报》2009年第6期18-24,共7页Journal of National University of Defense Technology

基　　金：国家自然科学基金资助项目(60873016);国家863计划资助项目(2009AA01Z102);教育部"高性能微处理器技术"创新团队资助项目(IRT0614)

摘　　要：动态差分逻辑是一种典型的电路级差分功耗攻击(DPA)防护技术。这种技术通过使逻辑门保持恒定的翻转率来降低电路功耗与数据信号之间的相关性。介绍了一种新型的、基于查找表(Look-Up-Table,LUT)结构的动态差分逻辑(LBDL),以及基于这种逻辑的集成电路设计方法。该设计方法仅需在传统的半定制设计流程中添加少量的替换操作就可以实现,因而比其他完全需要全定制设计的动态差分逻辑具有更好的实用性。而相对同样适用于半定制实现的动态差分逻辑WDDL(Wave Dynamic Differential Logic),LBDL逻辑解决了逻辑门翻转时刻与数据信号之间的相关性,从而比WDDL逻辑具有更好的功耗恒定性。实验结果表明,该设计方法能够有效实现具有抗DPA攻击性能的电路。Dynamic and differential logic styles are proposed as a typical differential power analysis （DPA） resistant technology. Because of the constant transition rate of dynamic and differential logic gates, the correlation between power consumption and signal values is significantly reduced. In this paper, a novel look-up-table （LUT） based differential logic （LBDL） and the design method based on this logic are presented. Instead of a full custom design, this method combines some modification with a regular standard cell design flow. Thus, have a better practicability. Unlike WDDL （Wave Dynamic Differential Logic）, which can also be implemented by standard cell design flow, the transition time of LBDL gates is independent of input values, hence power consumption of LBDL is more constant. Experimental results indicate that the LBDL-based design method can eliminates most of the power leakage.

关 键 词：安全芯片 DPA攻击 动态差分逻辑 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]