多标准可配置的视频编码亚像素插值结构  

A Multi-standard Configurable Sub-pixel Interpolation Architecture for Video Encoding

作　　者：谷会涛[1] 陈书明[1] 孙书为[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《国防科技大学学报》2009年第6期34-38,共5页Journal of National University of Defense Technology

基　　金：国家863计划资助项目(2007AA01Z108);教育部"高性能微处理器技术"创新团队资助项目(IRT0614)

摘　　要：针对视频编码中存在的各种不同的亚像素插值方法,提出了一种支持多种标准的可配置插值结构。该结构采用2个独立的8阶插值滤波器,每个滤波器配置一个独立参数寄存器,可灵活配置任意1/4像素位置的滤波系数,从而实现对各种亚像素插值方法的支持。2个滤波器采用两步法策略进行插值,可以减少约46%的计算量。采用SMIC 0.13μm CMOS标准单元工艺对该结构进行综合,其工作频率可以达到400MHz,面积约为32.6k门。实验结果显示,该滤波结构工作在250MHz时,可满足1920×1080、30fps的高清视频应用的实时插值计算。Various sub-pixd interpolation technologies are adopted in video coding applications. A multi-standard configuration interpolation architecture is proposed. It consists of two independent 8-tap filters. It can also reduce about 46% interpolation computation by a two-step filter method. Each filter includes a filter parameter register, which stores different filter parameter for various video standards. As a pipeline architecture, filter can have three filter results in one cycle. In SMIC 0.13μm CMOS process, the frequency of this architecture is up to 400MHz, and the area is about 32.6k gates. The experiment results show that, working on 250MHz, this architecture can satisfy the interpolation computation requirements of encoding 1920 × 1080,30fps HD video sequences.

关 键 词：亚像素插值 滤波器 运动估计 视频编码 多标准 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]