基于FPGA实现的DES抗能量攻击设计研究  

Design and research of DES against power analysis attacks based on FPGA

作　　者：温圣军[1] 张鲁国[1] 

机构地区：[1]解放军信息工程大学电子技术学院,郑州450004

出　　处：《计算机工程与应用》2010年第6期98-99,111,共3页Computer Engineering and Applications

基　　金：现代通信国家重点实验室基金资助资目(No.9140C1106030806)

摘　　要：针对文献[1]中提出的DES算法抗能量攻击设计方法,给出了对此方法的改进。改进后的设计方法与原方法相比,具有相同的能量攻击抵御能力。对改进算法的理论分析表明,此方法可适用于大多数分组密码算法的抗能量攻击设计,且相对于文献[1]中的方法,当基于FPGA具体实现时,改进算法可以在保持原有运行速度不变的情况下,节省约80%的硬件存储资源消耗。Aimed at the DES design method against power analysis attacks mentioned in reference [1],an improved one is proposed.Compared with the method of reference [1],it has the same ability against the power analysis attacks.By analyzing the improved algorithm in theory,it is applicable for this method to make use of in the process of most of cipher algorithm＇s design and implementation against power analysis attacks.The improved algorithm,while implemented based on FPGA,can not only save about eighty percent hardware storage resources,but also keep the operation rate in the same time.

关 键 词：三重数字加密标准算法(TDES) 能量攻击 逻辑资源 适用性 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]