AES密码芯片的相关性功耗分析仿真  

Simulation of correlation power analysis against AES cryptographic chip

作　　者：樊海锋[1] 严迎建[1] 徐金甫[1] 任方[1] 

机构地区：[1]解放军信息工程大学电子技术学院,河南郑州450004

出　　处：《计算机工程与设计》2010年第2期260-262,316,共4页Computer Engineering and Design

摘　　要：介绍了CMOS逻辑电路功耗泄露原理,建立了AES密码芯片运算时的功耗泄露模型,设计了相关性功耗分析(CPA)仿真方法。该方法根据部分猜测密钥的模拟功耗与整个正确密钥功耗之间的相关系数大小来确定猜测密钥的正确性,由此逐步推测整个密钥。仿真结果表明了未加防御措施的AES硬件面临CPA攻击时的脆弱性。The power leakage principle of CMOS device is introduced, power leakage model of AES is constructed and the simulation method of correlation power analysis is designed. With comparing the correlation index between the power consumption of guessed partial key and the real key, the validity of the guessed partial key is confirmed by this method, with the same method, the rest part of key is achieved. This method reveals the vulnerability of AES implementation without any countermeasure to CPA attacks.

关 键 词：高级加密标准 相关性功耗分析 仿真 功耗模型 汉明距 

分 类 号：TP309.2[自动化与计算机技术—计算机系统结构]