基于FPGA高动态GPS快速捕获协处理器设计实现  

Design of High Dynamic GPS Receiver Co-processor Based on FPGA

作　　者：赵慷慨[1] 汪峰[1] 李金海[1] 刘玫[1] 阎跃鹏[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《微电子学与计算机》2010年第2期38-40,44,共4页Microelectronics & Computer

摘　　要：高动态GPS接收机中,扩频信号捕获是系统的关键技术.由于系统的高动态特性,使GPS信号产生较大的载波多普勒频移和伪码多普勒频移,加大了信号捕获的难度.若采用通常的滑动相关捕获,需要很长的捕获时间;采用传统的全匹配滤波器结构,消耗的硬件资源太大.为提高捕获性能,分析了一种改进的折叠匹配滤波器并采用相干累加和非相干累加相结合的快速捕获方法,对GPS信号进行码相位的并行捕获,详细介绍了基于FPGA的具体实现.GPS signal acquisition is the key technology of high dynamic GPS receiver. For the high dynamic property, the signal has great Doppler effect, which makes the acquisition difficult. Under the circumstances, sliding correlation method makes too much time oonsumption, and it＇s unbearable; as to the traditional matched-filter, it＇s too much hardware cost. In this paper, we provide a new acquisition method, which is combining the modified fold-matched-filter with coherent integration and no-coherent integration. Some details in FPGA application were also introduced.

关 键 词：GPS 信号捕获 匹配滤波器 相干累加 非相干累加 

分 类 号：TP33[自动化与计算机技术—计算机系统结构]