可重构计算硬件平台的改进设计  

Improved Design of Reconfigurable Computing Hardware Platform

作　　者：王晟中[1] 陈伟男[1] 彭澄廉[1] 

机构地区：[1]复旦大学计算机科学技术学院,上海200433

出　　处：《计算机工程》2010年第5期250-252,共3页Computer Engineering

基　　金：国家自然科学基金资助项目(60573105)

摘　　要：针对现有可重构计算硬件平台配置时间长、灵活性受限的缺陷,提出一种改进设计。基于支持二维重构区域的Virtex-4现场可编程门阵列(FPGA)芯片,使重构模块放置更灵活、芯片面积利用率更高,通过将单片FPGA和外设集成在一块印刷电路板上,使系统的结构更紧凑,利用FPGA内嵌微处理器减轻通信和访存开销。调试结果表明,改进平台灵活性较高、功能和可扩展性更强。Aiming at the shortage of long configuration time and flexibility constrained for existing reconfigurable computing hardware platform, this paper proposes an improved design. Based on Virtex-4 Field Programmable Gate Array（FPGA） chip supporting 2D reconstructed area, it makes the module placement faster and higher utilization of chip area, makes more compact of system structure through integrating single FPGA and extras in a printing circuit diagram, uses FPGA embedded microprocessor to reduce cost of communication and access memory. Debugging result shows that improved platform is more flexible, function and extendibility is more strong.

关 键 词：可重构计算 部分可重构 动态可重构 现场可编程门阵列 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]