DDS+PLL高性能频率合成器的设计与实现  

Design and Realization of High Performance Frequency Synthesizer Based on DDS+PLL

作　　者：吴士云[1] 叶建芳[1] 石燚[1] 

机构地区：[1]东华大学信息科学与技术学院,上海201620

出　　处：《现代电子技术》2010年第5期81-83,共3页Modern Electronics Technique

摘　　要：结合DDS+PLL技术,采用DDS芯片AD9851和集成锁相芯片ADF4113完成了GSM 1 800 MHz系统中高性能频率合成器的设计与实现。详细介绍系统中核心芯片的性能、结构及使用方法,并运用ADS和ADISimPLL软件对设计方案进行仿真和优化,特别是滤波器的选择与设计。测试结果表明,该频率合成器具有高稳定度、高分辨率、低相位噪声的特点,达到了设计指标要求。In view of the respective advantages of the Direct Digital Frequency Synthesizer （DDS） and the integrated Phase Locked Loop （PLL） ,a high performance frequency synthesizer is designed which is used in GSM1800MHz. It is formed by the DDS chip AD9851 and the integrated phase- locked- chip ADF4113 using the DDS4-PLL technology. The performance, structure and application method of the core chip are introduced. At the same time, the simulation and optimization for the design proposal is made using ADS and ADISimPLL software. The filter is deliberately designed and selected. The simulation and optimized results prove that this frequency synthesizer has characteristics such as wideband, high resolution,and low phase noise. The test results meet the basic design requirements.

关 键 词：DDS PLL 频率合成 滤波器 

分 类 号：TN604[电子电信—电路与系统]