Physical Implementation of the 1GHz Godson-3 Quad-Core Microprocessor  

作　　者：范宝峡 杨梁 王江嵋 王茹 肖斌 徐英 刘动 赵继业 

机构地区：[1]Key Laboratory of Computer System and Architecture,Institute of Computing Technology,Chinese Academy of Sciences [2]Graduate University of Chinese Academy of Sciences [3]Loongson Technology,Corporation Limited

出　　处：《Journal of Computer Science & Technology》2010年第2期192-199,共8页计算机科学技术学报（英文版）

基　　金：supported by the National Basic Research 973 Program of China under Grant No.2005CB321600;the National High Technology Research & Development 863 Program of China under Grant Nos.2008AA110901,2009AA01Z125 and 2007AA01Z114;the National Natural Science Foundation of China under Grant Nos.60803029,60673146,60736012.

摘　　要：The Godson-3A microprocessor is a quad-core version of the scalable Godson-3 multi-core series. It is physically implemented based on the 65 nm CMOS process. This 174 mm2 chip consists of 425 million transistors. The maximum frequency is 1GHz with a maximum power consumption of 15 W. The main challenges of Godson-3A physical implementation include very large scale, high frequency requirement, sub-micron technology effects and aggressive time schedule. This paper describes the design methodology of the physical implementation of Godson-3A, with particular emphasis on design methods for high frequency, clock tree design, power management, and on-chip variation （OCV） issue.The Godson-3A microprocessor is a quad-core version of the scalable Godson-3 multi-core series. It is physically implemented based on the 65 nm CMOS process. This 174 mm2 chip consists of 425 million transistors. The maximum frequency is 1GHz with a maximum power consumption of 15 W. The main challenges of Godson-3A physical implementation include very large scale, high frequency requirement, sub-micron technology effects and aggressive time schedule. This paper describes the design methodology of the physical implementation of Godson-3A, with particular emphasis on design methods for high frequency, clock tree design, power management, and on-chip variation （OCV） issue.

关 键 词：physical implementation design methodology on-chip variation （OCV） low power clock tree 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]