Design and Application of Instruction Set Simulator on Multi-Core Verification  

作　　者：胡向东 郭勇 朱英 郭昕 王鹏 

机构地区：[1]National High Performance IC(Shanghai) Design Center

出　　处：《Journal of Computer Science & Technology》2010年第2期267-273,共7页计算机科学技术学报（英文版）

摘　　要：Instruction Set Simulator （ISS） is a highly abstracted and executable model of micro architecture. It is widely used in the fields of verification and debugging during the development of microprocessors. However, with the emergence of Chip Multi-Processors, the single-core ISS cannot meet the needs of microprocessor development. In this paper, we introduce our multi-core chip architecture first, after that a general methodology to expand a single-core ISS to a multi- core ISS （MCISS） is proposed. On this basis, a real-time comparison environment is created for multi-core verification, and the problems of multi-core communication and synchronization are addressed gracefully. With the ＂save and restore＂ mechanism, the verification procedure and the debugging are speeding up greatly.Instruction Set Simulator （ISS） is a highly abstracted and executable model of micro architecture. It is widely used in the fields of verification and debugging during the development of microprocessors. However, with the emergence of Chip Multi-Processors, the single-core ISS cannot meet the needs of microprocessor development. In this paper, we introduce our multi-core chip architecture first, after that a general methodology to expand a single-core ISS to a multi- core ISS （MCISS） is proposed. On this basis, a real-time comparison environment is created for multi-core verification, and the problems of multi-core communication and synchronization are addressed gracefully. With the ＂save and restore＂ mechanism, the verification procedure and the debugging are speeding up greatly.

关 键 词：processor design chip multi-processors （CMP） instruction set simulator （ISS） SIMULATION parallel stimulus 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]