基于FPGA的伪码快速搜索系统的研究与设计  

Research and Design of Pseudo-code Fast Search System Based on FPGA

作　　者：柳丰收[1] 羊彦[1] 张继光[1] 

机构地区：[1]西北工业大学电子信息学院,陕西西安710129

出　　处：《计算机测量与控制》2010年第2期430-433,共4页Computer Measurement &Control

基　　金：西北工业大学研究生创业种子基金资助(Z200941)

摘　　要：针对基于CDMA导频的无源定位系统所涉及的伪码搜索问题,提出利用先验信息加快伪码搜索速度的策略;依照该策略重点完成了伪码搜索系统的FPGA设计;该设计通过一个时序控制模块较好地解决了PN码发生器与算术逻辑单元的协调配合、PN码的捕获与跟踪、算术逻辑单元的分时复用等技术问题;通过Quartus Ⅱ与ModelSim的联合仿真,验证了该策略及其在FPGA设计中的正确性,同时表明了系统在-20dB的高斯白噪声干扰下,进行伪码搜索的时间小于100 ms,码片同步精度小于1/8码片宽度。Aiming at the pseudo-code search question involved by passive positioning system based on the CDMA pilot frequency, a strategy which uses some prior information to speed up the pseudo-code search speed is proposed. According to this strategy, a FPGA-based design of pseudo-code search system is completed. The problems of the coordination between PN code generator and the Arithmetic logic operation unit, PN code acquisition and tracking, time multiplexing of the arithmetic logic unit are solved. A co-simulation by Quartus Ⅱ and ModelSim shows the feasibility of this strategy and realization in FPGA. In the -20dB of Gaussian white noise interference, the co-simulation shows the pseudo-code search time of the system is less than lOOms and chip synchronization accuracy is less than 1 / 8 chip width.

关 键 词：FPGA 伪码搜索 无源定位系统 

分 类 号：TN962[电子电信—信号与信息处理]