相邻层走线的阻抗设计  

Impedance Design of the Transmission Line in Adjacent Layers

作　　者：陈婧[1] 

机构地区：[1]星网锐捷网络有限公司,福建福州350002

出　　处：《印制电路信息》2010年第3期46-49,共4页Printed Circuit Information

摘　　要：阻抗设计是高速PCB设计的一个重要组成部分。文章在简要介绍了传输线的阻抗计算原理的基础上,针对相邻层都有走线的情况,通过阻抗计算软件得出了叠层设计对阻抗影响的趋势规律。并在此基础上,设计了阻抗测试板,针对阻抗测试结果得出了相邻层的走线要符合阻抗匹配的设计规则。依据这些结论,就能够保证相邻层的走线阻抗符合设计值,因此对相邻层走线的阻抗设计有很好的指导性。Impedance design is an important part of the high-speed PCB design. This paper gives a brief introduction of the principal of transmission line impedance calculation, and focus on the case which has adjacent signal layers. It comes to the tendency of the impact on the impedance of the stack-up design through the impedance calculation software. Furthermore, it comes to the impedance matching design rules of the striplines in adjacent layers for the impedance test results. Based on these conclusions, we can ensure the characteristics impedance of adjacent layers with the design value. So it has a good guidance about the impedance design of adjacent signal layers.

关 键 词：带状线 特性阻抗 叠层 阻抗设计 

分 类 号：TN41[电子电信—微电子学与固体电子学]